環境：
硬件：PC機<------>ARM仿真器v8.00<------>已下載好bit流的Xinlinx SoC開發板（其上有arm cortex-a9核）
軟件：Redhat Linux6（或虛擬機） + openocd
使用openocd下載程序，調試arm cortex-a9核。
一、openocd安裝
- 下載libusb庫安裝或直接yum install libusb*
- 下載openocd-0.10.0.zip：https://sourceforge.net/projects/openocd/解壓，進入目錄
- $ ./configure --prefix=/home/benben/openocd --enable-jlink
- $ make #若編譯有錯根據提示信息修改
- $ sudo make install
二、openocd使用
$ lsusb
能查到仿真器usb信息...
$ openocd -f em8302_jtag.cfg（其中引用了jlink.cfg與v7arm.cfg） #連接開發板
打印出一些無Error的信息...
$ telnet localhost 4444 #啟動守護程序
> resume 0 #從0地址開始運行
> halt #暫停cpu
> mdw 0 12 #從0地址讀12個數（32位）
>mww 地址 寫的數 #向某地址寫數（32位）
>reg #查看寄存器
em8302_jtag.cfg內容
# The 8301 Board use jlink to Debug
source [find interface/jlink.cfg]
transport select jtag
# THe 8301 Board use a single v7arm chip
source [find target/v7arm.cfg]
echo "8302 Board Loaded."
# Set reset type and may be changed in some particular cases
reset_config trst_only
#reset_config separate
#reset_config trst_open_drain srst_open_drain
adapter_khz 200
# Wait after deasserting nTRST before starting new JTAG operations
#jtag_ntrst_delay 200
jlink.cfg內容（指定類型為jlink）
#
# Segger J-Link
#
# http://www.segger.com/jlink.html
#
interface jlink
# The serial number can be used to select a specific interface in case more than one
# is connected to the host.
#
# Segger software omits leading zeros in serial number displays,
# OpenOCD requires them.
#
# Example: Select J-Link with serial 123456789
#
# jlink serial 000123456789
v7arm.cfg（指定cpu信息）
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME ecictv7
}
# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
#
# Cortex A9 target
#
# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
# core 0 - 0x1fffc000
# core 1 - 0x2fffc000
set _TARGETNAME1 $_CHIPNAME.cpu.0
set _TARGETNAME2 $_CHIPNAME.cpu.1
# A9 core 0
target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80090000
# -coreid 0 -dbgbase 0xc0000000
#$_TARGETNAME1 configure -work-area-phys 0x80000000 -work-area-size 8096
$_TARGETNAME1 configure -event reset-start { adapter_khz 50 }
#$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
$_TARGETNAME1 configure -event gdb-attach { halt }
#smp mode cannot halt only one cpu core, have no idea, by yzq
# A9 core 1
#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
# -coreid 1 -dbgbase 0xc0002000
#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
#$_TARGETNAME2 configure -event gdb-attach { halt }
#target smp $_CHIPNAME.cpu.1 $_CHIPNAME.cpu.0
proc cycv_dbginit {target} {
# General Cortex A8/A9 debug initialisation
cortex_a dbginit
}