Signal in unit is connected to following multiple drivers VHDL

參考鏈接

https://blog.csdn.net/jbb0523/article/details/6946899

出錯原因

兩個Process都對LDS_temp進行了賦值，萬一在某個時刻，在兩個Process中對LDS_temp賦值條件都滿足，那么你讓FPGA該怎么做呢？讓它聽誰哪個Process塊的呢？

報錯

ISE14.7 綜合時報錯

ERROR:HDLCompiler:1401 - "D:\project\ISEProject\FlowingLED\LED.vhd" Line 23: Signal LDS_temp[7] in unit LED is connected to following multiple drivers:
Driver 0: output signal LDS_temp[7] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[7] of instance Latch (LDS_temp[7]).
Driver 0: output signal LDS_temp[6] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[6] of instance Latch (LDS_temp[6]).
Driver 0: output signal LDS_temp[5] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[5] of instance Latch (LDS_temp[5]).
Driver 0: output signal LDS_temp[4] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[4] of instance Latch (LDS_temp[4]).
Driver 0: output signal LDS_temp[3] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[3] of instance Latch (LDS_temp[3]).
Driver 0: output signal LDS_temp[2] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[2] of instance Latch (LDS_temp[2]).
Driver 0: output signal LDS_temp[1] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[1] of instance Latch (LDS_temp[1]).
Driver 0: output signal LDS_temp[0] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[0] of instance Latch (LDS_temp[0]).
--> 

出錯代碼

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Flowing LED
-- 先分頻再移位
entity LED is
	port(
	GCLK,BTNU:in std_logic;
	LDS:out std_logic_vector(7 downto 0)
	);
end LED;


architecture Behavioral of LED is
-- 計數
signal count:std_logic_vector(25 downto 0);
signal clk_temp:std_logic;
signal Q_temp:std_logic;
signal LDS_temp:std_logic_vector(7 downto 0):="00000001";
begin

	process(GCLK,BTNU)  
	--分頻系數
	variable N :std_logic_vector(25 downto 0):="10111110101111000010000000";
	begin  
		if BTNU='1' then
			count<="00000000000000000000000001"; 
			clk_temp<='1';	
			LDS_temp<= "00000001";
		elsif (GCLK'EVENT and GCLK='1')then 
			if (count=N)then
				count<="00000000000000000000000001";
				clk_temp<='1';
			else
				count<=count+1;
				clk_temp<='0';
			end if;
		end if;
	end process;
	--得到的clk_temp為2Hz，占空比1/50000000
	
	process(clk_temp)
	begin
		if (clk_temp'EVENT and clk_temp='1')then
			LDS_temp(7)<=Q_temp;
			LDS_temp(6 downto 0)<=LDS_temp(7 downto 1);
			--Q_temp<=LDS_temp(0);
		end if;
	end process;
	LDS<=LDS_temp;
end Behavioral;