參考博文：http://blog.sina.com.cn/s/blog_5ced60e80102y7pd.html
一顆健壯的IC芯片應該具有能屈能伸的品質，他需要適應於他所在應用范圍內變化的溫度、電壓，他需要承受制造工藝的偏差，這就需要在設計實現過程中考慮這些變化的溫度、電壓和工藝偏差。
在STA星球，用 library PVT、RC corner跟OCV來模擬這些不可控的隨機因素。在每個工藝結點，通過大量的建模跟實測，針對每個具體的工藝，foundary廠都會提供一張推薦的timingsignoff表格， 建議需要signoff的corner及各個corner需要設置的ocv跟margin。這些corner能保證大部分芯片可以承受溫度、電壓跟工藝偏差，一個corner=libraryPVT+ RC corner + OCV，本文將關注於library PVT。
P-process：IC制造工藝本身的不完美，使得制造偏差不可避免，在library中會用一個百分比來表示工藝偏差，如process:1表示沒偏差。在沉積或參雜過程中，雜質濃度密度、氧化層厚度、擴散深度都可能發生偏差，從而導致管子的電阻跟閾值電壓發生偏差；光刻過程中由於分辨率的偏差會導致管子的寬長比產生偏差。而這些偏差，都會導致管子性能的差異。
Network電容：
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耦合電容：Coupling capacitance=e*T/S
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表面電容：Surface capcitance=e*W/H
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邊緣電容：Fringe capcitance
決定容值的因素：
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介電常數：e
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線寬：W
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線厚：T
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線間距：S
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介電材料的厚度：H
隨着工藝進步，W, S, T 逐代遞減，表面電容跟隨減小，耦合電容隨之增加，耦合電容在總電容中占比增加，當線厚 T 一定時為了減少耦合電容要么增加線間距要么減小介電常數。通常為了減小噪聲敏感信號線（如clock net）上的耦合電容，在物理實現時會人為增加對應信號的線寬及線間距，俗稱NDR。要減小介電常數需要從材料入手，從 .18開始引入low K介電材料。
Network電阻：
R=r/W*T, r為電阻率，除了跟線寬 W 和線厚 T 相關之外，還跟溫度相關，隨着溫度的上升而增大。
| Parameters |
Resistance |
Surface Capacitance |
Coupling Capacitance |
| 溫度增加 |
增加 |
-- |
-- |
| 線寬減小 |
增加 |
減小 |
-- |
| 線厚減小 |
增加 |
-- |
減小 |
| 線間距減小 |
無影響 |
無影響 |
增加 |
由上面的分析可知，Network的單位電容和單位電阻是不可能同時最大或同時最小的。有了這些鋪墊，來看一下不同工藝結點是如何定義RC corner的。
90nm 之前，Cell delay占主導，Network電容主要是對地電容，STA只需要兩個RC corner即可：
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Cbest(Cmin): 電容最小電阻最大
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Cworst(Cmax):電容最大電阻最小
90nm 之后，netdelay的比重越來越大，而且network的耦合電容不可忽略，所以又增加了兩個RC corner:
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RCbest(XTALK corner): 耦合電容最大，（對地電容*電阻）最小
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RCworst(Delay corner): 耦合電容最小，（對地電容*電阻）最大
至此總共有兩個需要setup timing sign-off的RC corner，有四個需要hold timing sign-off的RC corner：
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Setup time sign-off 的RC corner是: Cworst / RCworst
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Hold time sign-off 的RC corner是: Cbest / RCbest / Cworst / RCworst
C-best:
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It hasminimum capacitance. So also known as Cmin corner.
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Interconnect Resistance is larger than the Typical corner.
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This corner results in smallest delay for paths with short nets and can be used for min-path-analysis.
C-worst:
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Refers tocorners which results maximum Capacitance. So also known as Cmax corner.
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Interconnect resistance is smaller than at typical corner.
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This corners results in largest delay for paths with shorts nets and can be used for max-path-analysis.
RC-best:
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Refers tothe corners which minimize interconnect RC product. So also known as RC-mincorner.
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Typicallycorresponds to smaller etch which increases the trace width. This results insmallest resistance but corresponds to larger than typical capacitance.
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Corner has smallest path delay for paths with long interconnects and can be used for min-path-analysis.
RC-worst:
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Refers tothe corners which maximize interconnect RC product. So also known as RC-maxcorner.
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Typicallycorresponds to larger etch which reduces the trace width. This results inlargest resistance but corresponds to smaller than typical capacitance.
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Corner has largest path delay for paths with long interconnects and can be used for max-path-analysis.
------C = a * W *L R = b *L/W RC = ab * L^2
所以對於短線來說（L很小），RC由於與L的平方成正比，非常小，電容起主要作用。對於長線RC起主要作用。
引入的DPT（Double Patterning Technology）之后，在同一層layer上要做兩次mask，兩次mask之間的偏差，會導致線間距變化，從而影響耦合電容值，需要將這一因素考慮到RC corner中，所以DPT 的RC corner是：Cworst_CCworst, RCworst_CCworst, Cbest_CCbest, RCbest_CCbest.
其中：
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Setup timesign-off 的RC corner是: Cworst_CCworst / RCworst_CCworst
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Hold timesign-off 的RC corner是: Cbest_CCbest / RCbest_CCbest / Cworst_CCworst /RCworst_CCworst
除以上這些corner外，還有一個corner叫Typical corner，對應於DPT的是Ctypical_CCworst, Ctypical_CCbest，這些corner不用於timing sign-off。
Q：還有一種RC corner 帶后綴『_T』，只用於setup signoff，T指的是什么？
A：T代表tighten，在rc的variation上的sigma分布比不帶T的更緊，因此只能用於setup，hold不推薦。Appleto Apple地比較，T的variation更小，理論看到的rc變化更小，單從setup產生violation的可能性更小。至於悲觀還是樂觀，除非自己定criteria，其余的follow foundry或者vendor的rule最重要。
Q：為什么setup既需要sign-off C-corner又需要sign-offRC-corner？
A：因為C-corner表示『電容』最大/最小，而RC-corner是『電容*電阻』最大/最小。通常對於短線而言，電容占主導地位，C-corner可以cover RC-corner，但對於長線則電阻占主導地位，C-corner無法cover RC-corner，而是反過來RC-corner去cover C-corner。而沒人保證一個設計里只有短線沒有長線，也沒權威對長短的幅度有量化的定義，所以最保險的就是兩者分別sign-off。
Q：為什么hold需要sign-off所有的corner？
A：對於hold而言，根據其仿真曲線，相互之間都無法完全覆蓋，故需要sign-off所有corner。
Q：金屬電阻是否跟density/spacing相關？為什么方塊電阻跟density/spacing相關？
A：就電阻本身而言，阻值跟density沒有關系，只跟金屬線自身的寬厚和電阻率相關，詳細描述：
There is no relationship between the density of a metal and itselectrical resistivity.
There is a big database of material properties called MatWeb which is recommend as a legitimate source of data by UCSD's and Stanford's library systems, Rose-Hulman, etc. I took data fromaround 60 different metals and graphed them:
As you can see there is no empirical relationship. From a theoryperspective, density has to do with atomic packing and resistivity has to dowith electronic structure.
Iwill admit, however, that gaseous copper is an extremely poor conductor.
但是，在半導體制造過程中，由於工藝偏差，電阻跟金屬線的density是相關的。此時，電阻率是線寬跟線間距的函數。這一關系，在foundry給的工藝文件里都有相應的描述，這些都是在抽RC時需要考慮的因素。
Resistivity as a Function of Width and Spacing (Rs = f(W) or rho=f(W,S))
Variationin resistivity is caused by a number of phenomena. Copper is a softer materialthan the dielectric in which it is embedded. As a result, the polishing of thewafer during the CMP process has a tendency to remove a little extra copperfrom the top of the wire. This effect is called dishing because of the shape ofthe resulting wire top. The effect becomes more pronounced as the wire widthincreases. This effect is shown in exaggerated form in following pic.
To reduce theeffect of dishing on wide wires, small holes, or slots, can be inserted atregular intervals in wide wires. These slots insert a form of hard"posts" in the wire so that the CMP process removes less copper. Thistechnique reduces the dishing, as well as the effective resistivity.
Anothercontributor to resistivity variation is the cladding in copper wires. Claddingis the material grown around the sides and bottom of copper wires to protectthem from chemical reactions with the dielectric material. This cladding isillustrated in gray in following pic. The thickness ofthe cladding on the sides and bottoms of wires also varies with the width of awire. Because cladding has a much higher resistance than copper, it impacts theeffective resistivity of copper wires. This effect is more pronounced in thenarrowest wires. The combination of the effects ofdishing, slotting, and cladding thickness is modeled by the wire resistivity asa function of the wire width in silicon, and its spacing.
Q：在《抽刀斷水水更流，RC Corner不再愁：STA之RC Corner》中說電阻跟spacing無關，在《一曲新詞酒一杯，RC Corner繼續飛: STA之RC Corner拾遺》又說電阻跟spacing有關，為什么電阻跟spacing就相關了？
A：就電阻本身是跟spacing沒有無關的，但在半導體制造過程中，因為銅軟，所以在dishing時會把銅線切掉一些，這跟那個范圍的金屬線密度相關，而且這個關系好像也不是線性的。線的密度不同，會使得制造過程對線的厚度造成的影響不同，線厚度被改變了，那阻值自然被改變了。在QRC抽RC的時候會把這一效應模擬成『電阻率=f(W,S)』。 這一效應在foundry給的工藝文件里有相應的描述。
@SteveB 后端角度？如果講RC 后端抽怎么考慮，講好原理以后剩下的就是按照RC corner 加上溫度抽，交給工具。如果想要知道原理，有幾個方面可以去考慮，也是一般后端拿到新工藝需要去研究的:
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對於寄生參數提取，相關的各個工具的技術文件怎么來？
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每個corner下的配合PVT signoff里的T趨勢如何，是否可以對signoff做精簡 ？
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double pattern multiple pattern 的影響如何？
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研究DFM。
當然還有其他，我這里想到比較能自己去學的有這些。
Q：通常說的ttcorner指的是啥？
A：@孟時光 ttcorner是指管子在tt+RCtyp吧。
Types of corners
When working in the schematic domain, we usually only work with front end of line (FEOL) process corners as these corners will affect the performance of devices. But there is an orthogonal set of process parameters that affect back end of line (BEOL) parasitics.
FEOL corners
One naming convention for process corners is to use two-letter designators, where the first letter refers to the N-channel MOSFET (NMOS) corner, and the second letter refers to the P channel (PMOS)corner. In this naming convention, three corners exist: typical, fast and slow. Fast and slow corners exhibit carrier mobilities that are higher and lower than normal,respectively. For example, a corner designated as FS denotes fast NFETs and slow PFETs.
There are therefore five possible corners:typical-typical (TT) (not really a corner of an n vs. p mobility graph, butcalled a corner, anyway), fast-fast (FF), slow-slow (SS), fast-slow (FS), andslow-fast (SF). The first three corners (TT, FF, SS) are called even corners,because both types of devices are affected evenly, and generally do notadversely affect the logical correctness of the circuit. The resulting devicescan function at slower or faster clock frequencies, and are often binned as such. The last two corners (FS, SF) are called "skewed"corners, and are cause for concern. This is because one type of FET will switchmuch faster than the other, and this form of imbalanced switching can cause oneedge of the output to have much less slew than the other edge. Latching devices may then record incorrect values in the logic chain.
BEOL corners
In addition to the FETs themselves, there are more on-chip variation (OCV) effects that manifest themselves at smaller technology nodes. These include process, voltage and temperature (PVT) variation effects on on-chip interconnect, as well as via structures.
Extraction tools often have a nominal corner to reflect the nominal cross section of the process target.Then the corners cbest and cworst were created to model the smallest and largest cross sections that are in the allowed process variation. A simple thought experiment shows that the smallest cross section with the largest vertical spacing will produce the smallest coupling capacitance. CMOS Digital circuits were more sensitive to capacitance than resistance so this variation was initially acceptable. As processes evolved and resistance of wiring became more critical, the additional rcbest and rcworst were created to model the minimum and maximum cross sectional areas for resistance.But the one change is that cross sectional resistance is not dependent on oxide thickness (vertical spacing between wires) so for rcbest the largest is used and for rcworst the smallest is used.
Parameters
Most importantly, the corners of a process are designated by five parameters
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Mobility variation due to implantation of N+ and P+
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Vth variation
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Resistance of the actives
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Body coefficient
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Oxide thickness
Other parameters like the effective Length, effective width, Cjsw caps, Cj caps also change.
注：所以TT corner並不是一個需要sign-off的corner。