vivado對task和function的可綜合支持

 

 手冊UG901,對vivado可綜合的語句支持進行了描述，HDL包括：verilog-2001，system-verilog，VHDL；

verilog-2001擴展了對task和function的支持。

ug901手冊中，章節7對支持的語法進行詳細描述。

                                  

 

Filename: functions_1.v
//
// An example of a function in Verilog
//
// File: functions_1.v
//
module functions_1 (A, B, CIN, S, COUT);
  input [3:0] A, B;
  input CIN;
  output [3:0] S;
  output COUT;
  wire [1:0] S0, S1, S2, S3;
     function signed [1:0] ADD;
      input A, B, CIN;
      reg S, COUT;
      begin
          S    = A ^ B ^ CIN;
          COUT = (A&B) | (A&CIN) | (B&CIN);
          ADD  = {COUT, S};
      end
    endfunction
    
assign S0 = ADD (A[0], B[0], CIN),
       S1 = ADD (A[1], B[1], S0[1]),
       S2 = ADD (A[2], B[2], S1[1]),
       S3 = ADD (A[3], B[3], S2[1]),
       S  = {S3[0], S2[0], S1[0], S0[0]},
       COUT = S3[1];
endmodule

 

Filename: task_1.v
// Verilog tasks
// tasks_1.v
//
module tasks_1 (A, B, CIN, S, COUT);
   input [3:0] A, B;
   input CIN;
   output [3:0] S;
   output COUT;
   reg [3:0] S;
   reg COUT;
   reg [1:0] S0, S1, S2, S3;
   
  task ADD;
      input A, B, CIN;
      output [1:0] C;
      reg [1:0] C;
      reg S, COUT;
        begin
           S    = A ^ B ^ CIN;
           COUT = (A&B) | (A&CIN) | (B&CIN);
           C    = {COUT, S};
        end
  endtask
  
always @(A or B or CIN)
   begin
       ADD (A[0], B[0], CIN, S0);
       ADD (A[1], B[1], S0[1], S1);
       ADD (A[2], B[2], S1[1], S2);
       ADD (A[3], B[3], S2[1], S3);
       S    = {S3[0], S2[0], S1[0], S0[0]};
       COUT = S3[1];
   end
   
endmodule

 

Filename: asym_ram_tdp_read_first.v
// Asymetric RAM - TDP
// READ_FIRST MODE.
// asym_ram_tdp_read_first.v

module asym_ram_tdp_read_first 
        (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);

parameter WIDTHB     = 4;
parameter SIZEB      = 1024;
parameter ADDRWIDTHB = 10;
parameter WIDTHA     = 16;
parameter SIZEA      = 256;
parameter ADDRWIDTHA = 8;

   input                  clkA;
   input                  clkB;
   input                  weA, weB;
   input                  enaA, enaB;
   input [ADDRWIDTHA-1:0] addrA;
   input [ADDRWIDTHB-1:0] addrB;
   input [WIDTHA-1:0]     diA;
   input [WIDTHB-1:0]     diB;
   output [WIDTHA-1:0]     doA;
   output [WIDTHB-1:0]     doB;
   
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}

function integer log2;
  input integer value;
  reg [31:0] shifted;
  integer res;
     begin
        if (value < 2)
           log2 = value;
        else
           begin
              shifted = value-1;
              for (res=0; shifted>0; res=res+1)
                 shifted = shifted>>1;
                 log2    = res;
           end
     end
endfunction



localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHA-1:0] readA;
reg [WIDTHB-1:0] readB;

  always @(posedge clkB)
    begin
      if (enaB) begin
        readB <= RAM[addrB] ;
        if (weB)
          RAM[addrB] <= diB;
        end
    end
    
always @(posedge clkA)
   begin : portA
        integer i;
        reg [log2RATIO-1:0] lsbaddr ;
        for (i=0; i< RATIO; i= i+ 1) begin
           lsbaddr = i;
           if (enaA) begin
                 readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}];
               if (weA)
                 RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
           end
        end
   end
   
assign doA = readA;
assign doB = readB;
endmodule

 

 

 veriilog對常量、結構和編譯指令的支持：

Verilog constant
force	Unsupported
release	Unsupported
forever statements	Unsupported
repeat statements	Supported, but repeat value must be constant
for statements	Supported, but bounds must be static
delay (#)	Ignored
event (@)	Unsupported
wait	Unsupported
named events	Unsupported
parallel blocks	Unsupported
specify blocks	Ignored
disable	Supported except in For and Repeat Loop statements
Verilog Design Hierarchies
module definition	Supported
macromodule definition	Unsupported
hierarchical names	Supported
defparam	Supported
array of instances	Supported
Verilog Compiler Directives
`celldefine `endcelldefine	Ignored
`default_nettype	Supported
`define	Supported
`ifdef `else `endif	Supported
`undef, `ifndef, `elsif	Supported
`include	Supported
`resetall	Ignored
`timescale	Ignored
`unconnected_drive `nounconnected_drive	Ignored
`uselib	Unsupported
`file, `line	Supported