基於MATLAB2016b圖形化設計自動生成Verilog語言的積分模塊及其應用

 

 

        在電力電子變流器設備中，常常需要計算發電量，由於電力電子變流器設備一般是高頻變流設備，所以發電量的計算幾乎時實時功率的積分，此時就會用到一個積分模塊。發電量計算的公式如下：Q=∫P。

      FPGA由於其並行處理的運算方式，使其在電力電子領域的應用越來越廣泛，有專家斷言，DSP能做的事情，FPGA都可以做。

此外，MATLAB2016bb在圖形化設計算法自動生成代碼上做了大量優化，使算法開發的時間大大縮小，下面共享一個基於MATLAB2016b圖形化設計自動生成Verilog語言的積分模塊及其應用。

1 在MATLAB2016b中嗎，模塊的封裝如下圖所示。

接口定義如下：

Integration_Input_b20——需要積分的量，比如在電力電子變流設備中的有功功率P，單位位W，是一個20位寬的有符號數，范圍[-2^(19),(2^19-1)];

Integration_En——積分使能信號，僅該位置1模塊方進行積分運算。

UpLimit_b32 和 LowLimit_b32——積分上限與下限限制，位寬位32的有符號數。

Pulse_4096Hz——該脈沖頻率是積分頻率，即1s時間內積分4096次，則可以滿足時時積分要求。

Point01kWH_b32——發電量單位：0.01度（1度=1kW*H）。

Point1kWH_b30——發電量單位：0.1度（1度=1kW*H）。

Ws_for0p01kWH_Cycle_b20——該位主要觀察在0.01度的周期內來回顯示時時電量，每0.01度就刷新一次。

 

2 在MATLAB2016b中嗎，模塊並行圖形化設計如下圖所示。

3 在MATLAB2016b中自動生成可應用的Verilog語言代碼如下：

// -------------------------------------------------------------
// 
// File Name: F:\TongJingRen\Energy Production Calculation by TongJingRen\Simulation_Model_Base_Platform20180211\Energy_Production_Calculation_by_TongJingRen.v
// Created: 2018-02-27 11:32:09
// 
// Generated by MATLAB 9.1 and HDL Coder 3.9
// 
// 
// -- -------------------------------------------------------------
// -- Rate and Clocking Details
// -- -------------------------------------------------------------
// Model base rate: 6.4e-07
// Target subsystem base rate: 6.4e-07
// 
// -------------------------------------------------------------


// -------------------------------------------------------------
// 
// Module: Energy_Production_Calculation_by_TongJingRen
// Source Path: Simulation_Model_Base_Platform20180211/Energy Production Calculation by TongJingRen
// Hierarchy Level: 0
// 
// -------------------------------------------------------------

`timescale 1 ns / 1 ns

module Energy_Production_Calculation_by_TongJingRen
          (
           g_clk,
           Rst_n,
           Integration_Input_b20,
           Integration_En,
           UpLimit_b32,
           LowLimit_b32,
           Pulse_4096Hz,
           Point01kWH_b32,
           Point1kWH_b30,
           Ws_for0p01kWH_Cycle_b20
          );



  input   g_clk;
  input   Rst_n;
  input   signed [19:0] Integration_Input_b20;  // sfix20
  input   Integration_En;
  input   signed [31:0] UpLimit_b32;  // int32
  input   signed [31:0] LowLimit_b32;  // int32
  input   Pulse_4096Hz;
  output  signed [31:0] Point01kWH_b32;  // int32
  output  signed [29:0] Point1kWH_b30;  // sfix30
  output  signed [19:0] Ws_for0p01kWH_Cycle_b20;  // sfix20

  wire OR4_out1;
  wire switch_compare_1;
  wire signed [19:0] Switch43_out1;  // sfix20
  reg signed [31:0] Unit_Delay1_out1;  // int32
  wire signed [31:0] Switch28_out1;  // int32
  wire signed [31:0] Switch1_out1;  // int32
  wire Relational_Operator2_relop1;
  wire signed [31:0] Switch4_out1;  // int32
  wire signed [31:0] Add8_1;  // sfix32
  wire signed [31:0] Add8_out1;  // int32
  wire RO13_relop1;
  wire signed [31:0] Switch41_out1;  // int32
  wire RO14_relop1;
  wire signed [31:0] Switch42_out1;  // int32
  wire [19:0] Bit_Slice9_out1;  // ufix20
  wire signed [19:0] Data_Type_S6_out1;  // sfix20
  wire CT1_out1;
  wire signed [19:0] Switch2_out1;  // sfix20
  reg signed [19:0] Unit_Delay4_out1;  // sfix20
  reg signed [31:0] Unit_Delay3_out1;  // int32
  wire signed [31:0] Add1_out1;  // int32
  wire signed [31:0] Switch3_out1;  // int32
  wire signed [40:0] Divide_out1;  // sfix41
  wire [29:0] Bit_Slice1_out1;  // ufix30
  wire signed [29:0] Data_Type_S1_out1;  // sfix30


  assign OR4_out1 = Integration_En & Pulse_4096Hz;



  assign switch_compare_1 = OR4_out1 > 1'b0;



  assign Switch43_out1 = (switch_compare_1 == 1'b0 ? 20'sb00000000000000000000 :
              Integration_Input_b20);



  assign Switch1_out1 = (Integration_En == 1'b0 ? Unit_Delay1_out1 :
              Switch28_out1);



  always @(posedge g_clk)
    begin : Unit_Delay1_process
      if (Rst_n == 1'b0) begin
        Unit_Delay1_out1 <= 32'sb00000000000000000000000000000000;
      end
      else begin
        Unit_Delay1_out1 <= Switch1_out1;
      end
    end



  assign Switch4_out1 = (Relational_Operator2_relop1 == 1'b0 ? Unit_Delay1_out1 :
              32'sb00000000000000000000000000000000);



  assign Add8_1 = {{12{Switch43_out1[19]}}, Switch43_out1};
  assign Add8_out1 = Add8_1 + Switch4_out1;



  assign RO13_relop1 = Add8_out1 > UpLimit_b32;



  assign Switch41_out1 = (RO13_relop1 == 1'b0 ? Add8_out1 :
              UpLimit_b32);



  assign RO14_relop1 = Switch41_out1 < LowLimit_b32;



  assign Switch42_out1 = (RO14_relop1 == 1'b0 ? Switch41_out1 :
              LowLimit_b32);



  assign Switch28_out1 = (Integration_En == 1'b0 ? 32'sb00000000000000000000000000000000 :
              Switch42_out1);



  assign Bit_Slice9_out1 = Switch28_out1[31:12];



  assign Data_Type_S6_out1 = Bit_Slice9_out1;



  assign CT1_out1 = Data_Type_S6_out1 >= 20'sb00001000110010100000;



  assign Switch2_out1 = (CT1_out1 == 1'b0 ? Data_Type_S6_out1 :
              20'sb00001000110010100000);



  always @(posedge g_clk)
    begin : Unit_Delay4_process
      if (Rst_n == 1'b0) begin
        Unit_Delay4_out1 <= 20'sb00000000000000000000;
      end
      else begin
        Unit_Delay4_out1 <= Switch2_out1;
      end
    end



  assign Relational_Operator2_relop1 = Unit_Delay4_out1 >= 20'sb00001000110010100000;



  assign Add1_out1 = 32'sb00000000000000000000000000000001 + Unit_Delay3_out1;



  assign Switch3_out1 = (Relational_Operator2_relop1 == 1'b0 ? Unit_Delay3_out1 :
              Add1_out1);



  always @(posedge g_clk)
    begin : Unit_Delay3_process
      if (Rst_n == 1'b0) begin
        Unit_Delay3_out1 <= 32'sb00000000000000000000000000000000;
      end
      else begin
        Unit_Delay3_out1 <= Switch3_out1;
      end
    end



  assign Point01kWH_b32 = Unit_Delay3_out1;

  assign Divide_out1 = Unit_Delay3_out1 * 9'sb011001101;



  assign Bit_Slice1_out1 = Divide_out1[40:11];



  assign Data_Type_S1_out1 = Bit_Slice1_out1;



  assign Point1kWH_b30 = Data_Type_S1_out1;

  assign Ws_for0p01kWH_Cycle_b20 = Data_Type_S6_out1;

endmodule  // Energy_Production_Calculation_by_TongJingRen