Quartus14.1中Qsys創建custom component時編譯出錯原因

利用Quartus14.1中Qsys工具新建自定義組件時會產生“part-select direction is opposite from prefix index direction”錯誤，這是由於Qsys生成自定義組件的地址空間時沒有考慮hw.tcl文件中限定的地址空間范圍，而是按照可用的最大地址空間進行分配導致的。

例如我的自定義組件使用PAD0進行通道選擇，而Qsys為PAD0分配了可用的最大地址空間，和其他組件地址空間發生了重疊。

localparam ADDR_RANGE = 64'h40000;//最大地址空間

    localparam PAD0 = log2ceil(64'h40000 - 64'h0); //地址空間錯誤
2     localparam PAD1 = log2ceil(64'h10008 - 64'h10000); 
    localparam PAD2 = log2ceil(64'h10050 - 64'h10040); 
    localparam PAD3 = log2ceil(64'h10090 - 64'h10080); 
    localparam PAD4 = log2ceil(64'h100d0 - 64'h100c0); 
    localparam PAD5 = log2ceil(64'h20008 - 64'h20000);

    localparam ADDR_RANGE = 64'h40000;
    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
                                  (RANGE_ADDR_WIDTH == 0) ?
                                        PKT_ADDR_H :
                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;

    localparam RG = RANGE_ADDR_WIDTH-1;

 if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0   ) begin //編譯錯誤在此產生
            src_channel = 8'b100000;
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
 end

在計算通道選擇時RG的值小於PAD0，這樣會導致編譯器輸出“part-select direction is opposite from prefix index directio”錯誤（見參考文獻2）。

解決方法：

修改

//修正對應的PAD*地址
localparam PAD0 = log2ceil(64'h10000 - 64'h0);

 

參考文獻：

1.http://www.alterawiki.com/wiki/New_Qsys_Issues中Merlin Address Routers for Custom peripherals，內容如下：

Merlin Address Routers for Custom peripherals
Issue: When generating the system, Merlin address routers are generated ignoring the ExplicitAddressSpan Avalon property. This causes channels to be greater than the complete address space in some cases; for instance, for a system that uses 29 bits of address space (512 MBs), with explicitly using only 16 MBs, Merlin address routers are generated with full 29 bits of address space per channel. Since the complete address space defaults to the size of the address space of the biggest addressable peripheral, this later causes errors in compilation (Verilog errors containing "...part-select direction is opposite from prefix index direction...") and also address space is overlapped with other peripherals with smaller address spaces.
Workaround: Manually edit nios_addr_router.sv files (there will be more of them; they are located under \{nios_name}\synthesis\submodules\ directory in your project directory) and manually set the values of the PADx variables to the desired address space size (ExplicitAddressSpanValue = 2^PADxValue). Do not change the value of the complete address space (RG variable), as this might introduce more problems.

2.http://quartushelp.altera.com/14.0/mergedProjects/msgs/msgs/evrfx2_veri_opposite_direction.htm，內容如下：

Verilog HDL error at <location>: part-select direction is opposite from prefix index direction

(ID: 13437)

---

CAUSE:

In a Verilog Design File (.v) at the specified location, you used a part-select to select a part of a vector; however, in the part-select, the direction from MSB to LSB is reversed from the direction in the declaration of the vector. For example, see the following excerpt of a sample design, which uses a part-select on vector: module veri_test(in, out); input [3:0] in; output [1:0] out; assign out = in[0:1]; endmodule

ACTION:

Use the same direction in the part-select of a vector as is used in the declaration of the vector. For example, in the previous sample design, you can change the assignment to out into the following format: assign out = in[1:0];

See also:

Section 4 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual