彩色陰極射線管的剖面圖:
1. 電子QIANG Three Electron guns (for red, green, and blue phosphor dots)
2. 電子束 Electron beams
3. 聚焦線圈 Focusing coils
4. 偏向線圈 Deflection coils
5. 陽極接點 Anode connection
6. Mask for separating beams for red, green, and blue part of displayed image
7. 熒光粉層 Phosphor layer with red, green, and blue zones
8. Close-up of the phosphor-coated inner side of the screen
陰極射線管
陰極射線管（Cathode ray tube，縮寫：CRT，又稱“顯像管”、布勞恩管）是一種用於顯示系統的物理儀器，
曾廣泛應用於示波器、電視機和顯示器上。它是利用陰極電子qiang發射電子，在陽極高壓的作用下，射向螢光屏，使螢光粉發光，
同時電子束在偏轉磁場的作用下，作上下左右的移動來達到掃描的目的。
早期的陰極射線管僅能顯示光線的強弱，展現黑白畫面。
而彩色陰極射線管具有紅、綠色和藍色三支電子QIANG，三支電子QIANG同時發射電子打在屏幕玻璃上磷化物上來顯示顏色。
由於它笨重、耗電且較占空間，2000年代起幾乎被輕巧、省電且省空間的液晶顯示器取代。
陰極射線管的市場剩下極重視色彩表現及低溫環境下等特殊用途。
最早的陰極射線管是由英國人威廉·克魯克斯首創，可以發出射線，這種陰極射線管被稱為克魯克斯管。
德國人卡爾·費迪南德·布勞恩在陰極射線管上塗布螢光物質，
此種陰極射線顯像管被稱為布勞恩管，在德國、日本等地，仍廣泛使用布勞恩管這一稱呼。
顯像管的種類
- 磁場偏向型：以磁場令電子束產生偏向，產生磁場的偏向線圈附加在陰極射線管頸部外側。
電視機使用此種方式的顯像管。 - 電場偏向型：以電場令電子束產生偏向，產生電場的偏向極板內建在陰極射線管內部。
示波器使用此種方式的顯像管，以利應付不同的掃描頻率，但此方式需要較長的管身。 - 威廉士管：具有記憶保持功能的特殊陰極射線管。
CRT顯示器的視頻帶寬可以看做每秒鍾所掃描的像素點數的總和，一般采用MHz（兆赫茲）為單位。
眾所周知，CRT顯示器是靠電子束激發屏幕內表面的熒光粉來顯示圖像的，
由於熒光粉被點亮后很快會熄滅，所以電子QIANG必須循環地不斷激發這些點。
屏幕分辨率越高，需要掃描的點數就越多，對電子QIANG掃描頻率的要求就更高，視頻帶寬也因此需要提高。
一般來說，CRT顯示器工作頻率范圍在電路設計時就已經固定了，主要取決於高頻放大部分元件的特性，
由於高頻電路的設計相對困難，因此成本也較高，同時還會產生一定的輻射。
對於CRT顯示器而言，高頻處理能力越好，視頻帶寬所能達到的頻率越高，圖像穩定性也越好。
CRT顯示器對視頻帶寬的要求，除了分辨率外，還和它的場頻有密切的關系。
場頻是指CRT顯示器屏幕每秒鍾刷新的次數，又稱為垂直掃描頻率。
當場頻過低時，人眼會感覺到屏幕有明顯的閃爍，圖像穩定性差，容易造成眼睛疲勞。
一般來講，CRT顯示器屏幕的場頻要達到75Hz以上人眼才不易出現閃爍感，但長時間注視必然會讓眼睛感到很累。
此外，視頻帶寬不僅對顯示器壽命和故障率有影響，還對顯示器品質有重要影響。
如果顯示器實際帶寬不足以支持用戶設定的分辨率和場頻，則會使顯示的清晰度受到影響，從而影響顯示效果。
顯示器對帶寬的要求可以用分辨率與場頻來計算：帶寬要求等於“水平分辨率×垂直分辨率×場頻”。
CRT顯示器(學名為“陰極射線顯像管”)是就是這樣一種裝置，它主要由電子QIANG(Electron gun)、
偏轉線圈(Deflection coils)、蔭罩(Shadow mask)、熒光粉層(phosphor)和玻璃外殼五部分組成。
其中我們印象最深的肯定是玻璃外殼，也可以叫做熒光屏，因為它的內表面可以顯示豐富的色彩圖像和清晰的文字。
CRT顯示器是怎樣將三原色原理用在其中。當然，並不是直接將這三原色畫在熒光屏上，而是用電子束來進行控制和表現的。
1、電子QIANG是如何工作的
這首先有賴於熒光粉層，在熒光屏上塗滿了按一定方式緊密排列的紅、綠、藍三種顏色的熒光粉點或熒光粉條，
稱為熒光粉單元，相鄰的紅、綠、藍熒光粉單元各一個為一組，學名稱之為像素。
每個像素中都擁有紅、綠、藍(R、G、B)三原色，根據我們剛才所說的三原色理論，這就有了形成千變萬化色彩的基礎。
然而，怎樣把這三原色混合成豐富的色彩。
我們通過電子QIANG(Electron gun)來解決這個問題，沒錯，電子QIANG就好像手QIANG一樣，可以發射，不過發射的不是子彈，而是非常高速的電子束。
其工作原理是由燈絲加熱陰極，陰極發射電子，然后在加速極電場的作用下，經聚焦極聚成很細的電子束，
在陽極高壓作用下，獲得巨大的能量，以極高的速度去轟擊熒光粉層。
這些電子束轟擊的目標就是熒光屏上的三原色。為此，電子QIANG發射的電子束不是一束，而是三束，
它們分別受電腦顯卡R、 G、 B三個基色視頻信號電壓的控制，去轟擊各自的熒光粉單元。
受到高速電子束的激發，這些熒光粉單元分別發出強弱不同的紅、綠、藍三種光。
根據空間混色法(將三個基色光同時照射同一表面相鄰很近的三個點上進行混色的方法)產生豐富的色彩，
這種方法利用人們眼睛在超過一定距離后分辨力不高的特性，產生與直接混色法相同的效果。
用這種方法可以產生不同色彩的像素，而大量的不同色彩的像素可以組成一張漂亮的畫面，而不斷變換的畫面就成為可動的圖像。
很顯然，像素越多，圖像越清晰、細膩，也就更逼真。可是，怎樣用電子QIANG來同時激發這數以萬計的像素發光並形成畫面。
2、畫面是如何形成的
科學家們想到了一個很聰明的辦法，其原理是利用了人們眼睛的視覺殘留特性和熒光粉的余輝作用，
這就是我們即使只有一支電子QIANG，只要我們的三支電子束可以足夠快地向所有排列整齊的像素進行激發，
我們還是可以看到一幅完整的圖像的。大家不要懷疑，我們現在的CRT顯示器中的電子QIANG能發射這三支電子束，
然后以非常非常快的速度對所有的像素進行掃描激發。要形成非常高速的掃描動作，我們還需要偏轉線圈(Deflection coils)的幫助，
通過它，我們可以使顯像管內的電子束以一定的順序，周期性地轟擊每個像素，使每個像素都發光，而且只要這個周期足夠短，
也就是說對某個像素而言電子束的轟擊頻率足夠高，我們就會看到一幅完整的圖像。
我們把這種電子束有規律的周期性運動叫掃描運動。
3、顯示器的掃描方式
理解了三原色，聰明的你一定會想到，可以用這樣一個原理來制作彩色顯示器呀。
沒錯，我們今天的色彩豐富的CRT顯示器正是由這個三原色原理制造出來的。
剛才提到，三原色的選擇在原則上是任意的，但是通過實驗研究發現，
人們的眼睛對紅、綠、藍三種顏色反應最靈敏，而且它們的配色范圍比較廣，
用這三種顏色可以隨意配出自然界中的大部分顏色，
因此在CRT顯示器中，選用紅、綠、藍三種顏色作為三原色，
還分別用R、G、B三個字母來表示。
現在問題來了，怎樣可以把這三原色的光表現出來呢，我們需要一個機電裝置來完成這一表現過程。
沒錯，因為有大量排列整齊的像素需要激發，必然要求有規律的電子QIANG掃描運動才顯得高效，通常實現掃描的方式很多，
如直線式掃描，圓形掃描，螺旋掃描等等。其中，直線式掃描又可分為逐行掃描和隔行掃描兩種，
相信大家都經常聽到，事實上，在CRT顯示系統中兩種都有采用。
逐行掃描是電子束在屏幕上一行緊接一行從左到右的掃描方式，是比較先進的一種方式。
而隔行掃描中，一張圖像的掃描不是在一個場周期中完成的，而是由兩個場周期完成的。
在前一個場周期掃描所有奇數行，稱為奇數場掃描，在后一個場周期掃描所有偶數行，稱為偶數場掃描。
無論是逐行掃描還是隔行掃描，為了完成對整個屏幕的掃描，掃描線並不是完全水平的，
而是稍微傾斜的，為此電子束既要作水平方向的運動，又要作垂直方向的運動。
前者形成一行的掃描，稱為行掃描，后者形成一幅畫面的掃描，稱為場掃描。
有了掃描，就可以形成畫面，然而在掃描的過程中，怎樣可以保證三支電子束准確擊中每一個像素。
這就要借助於蔭罩(Shadow mask)，它的位置大概在熒光屏后面(從熒光屏正面看)約10mm處，
厚度約為0.15mm的薄金屬障板，它上面有很多小孔或細槽，它們和同一組的熒光粉單元即像素相對應。
三支電子束經過小孔或細槽后只能擊中同一像素中的對應熒光粉單元，因此能夠保證彩色的純正和正確的會聚，
所以我們才可以看到清晰的圖像。至於畫面的連續感，則是由場掃描的速度來決定的，場掃描越快，
形成的單一圖像越多，畫面就越流暢。
而每秒鍾可以進行多少次場掃描通常是衡量畫面質量的標准，我們通常用幀頻或場頻(單位為Hz，赫茲)來表示，
幀頻越大，圖像越有連續感。我們知道，24Hz場頻是保證對圖像活動內容的連續感覺，48Hz場頻是保證圖像顯示沒有閃爍的感覺，
這兩個條件同時滿足，才能顯示效果良好的圖像。
其實，這就跟動畫片的形成原理是相似的，一張張的圖片快速閃過人的眼睛，就形成連續的畫面，就變成動畫。
什么叫光柵掃描
光柵掃描顯示器顯示圖形時，電子束依照固定的掃描線和規定的掃描順序進行掃描。
電子束先從熒光屏左上角開始，向右掃一條水平線，然后迅速地回掃到左邊偏下一點的位置，
再掃第二條水平線，照此固定的路徑及順序掃下去，直到最后一條水平線，即完成了整個屏幕的掃描。
Displaying a picture
H-SYNC & V-SYNC Pulse Signals
Try and view the H-SYNC and V-SYNC signals like Custom "COUNTERS"
that are constantly running and counting up to their MAXIMUM declared value,
resetting to zero and then counting up once again.
Every time the H-SYNC counter resets to zero, the V-SYNC counter is only incremented by 1.
The animated GIF Image shown below shows how the H-SYNC & V-SYNC signals are used together to create the Screen Refresh Cycle.
When you look at these signals like (X & Y) counters, they essentially count through each Pixels on the screen
from the Top Left corner all the way down in sequence to the Bottom Right corner.
This process repeats 60 times per second, due to the fact that we are using a 60Hz refresh rate.
The H-SYNC and V-SYNC signal patterns that we send to the VGA monitor,
when working together, they create the Zig-Zag scanning effect as shown below.
Now, depending on the Frequency, Pulse Width and Duty Cycle of these signal patterns...
we can create different resolution settings for the monitor to display.
So we have a specific H-SYNC and V-SYNC signal Pattern for creating the Zig-Zag scanning cycle of a 640 X 480 screen resolution,
and we also have another H-SYNC and V-SYNC signal Pattern for a 1600 X 1200 screen resolution, and many more.
The Image above is actually showing what's called Interlaced Frames.
You don't really need to worry about that right now, as we are not using this particular format.
The animated image is mainly being used to show you the basic concept of a screen "Refresh Cycle".
Now the fact that we are using a resolution setting of (640 x 480) this means that we have 640 Pixels
that run from the left side of our screen to the Right Side.
This also means that we have 480 Pixels that run from the Top of the screen to the Bottom.
In other words, what we have here is a 640 X 480 Pixel Matrix.
You can consider the Top Left corner of the Screen as the starting point for your H-SYNC and V-SYNC counters starting at Zero.
The H-SYNC Counter then proceeds to increment through all 640 pixels on the first horizontal row from Left to Right.
Once it reaches the end of the Row, it then resets to the beginning.
However this time, it also moves down by one pixel to the next Row and increments the V-SYNC counter by 1.
This process is repeated until the V-SYNC counter counts to 479, which brings it to the last Row at the Bottom of the screen.
Then, when the H-SYNC counter reaches the last pixel on the Bottom Right corner of the Screen (639),
both the H-SYNC and V-SYNC counters are reset to Zero.
This brings us back to the Top Left corner pixel and the entire counting Process starts all over again.
A single pass over the entire screen is called a "Screen Refresh Cycle" and this is repeated 60 times per second
to refresh the screen and update each pixel for a particular color... and in turn, this produces an Image on the screen.
Review the Animated GIF image above to get a better understanding of this "Screen Refresh" process in action.
A CRT television displays an image by scanning a beam of electrons
across the screen in a pattern of horizontal lines known as a raster.
At the end of each line the beam returns to the start of the next line;
at the end of the last line it returns to the top of the screen.
As it passes each point the intensity of the beam is varied,
varying the brightness (technically, luminance) of that point.
A color television system is identical except that an additional signal
known aschrominance controls the color of the spot.
Raster scanning is shown in a slightly simplified form below.
When analog television was developed, no affordable technology for storing any video signals existed;
the luminance signal has to be generated and transmitted at exactly the point in time at which is displayed on the CRT.
It is therefore essential to keep the raster scanning in the camera (or other device for producing the signal)
in exact synchronization with the scanning in the television.
The physics of the CRT require that a finite time interval is allowed
for the spot to move back to the start of the next line (horizontal retrace)
or the start of the screen (vertical retrace).
The timing of the luminance signal must allow for this.
Raster scanning has to be performed sufficiently quickly that persistence of vision allows the eye
to view a stable image, and such that moving images can be displayed without appearing jerky.
The maximum frame rate achievable depends on the bandwidth of the electronics and transmission system,
and the number of lines in the image. In practice, a rate of 50 or 60 hertz is a satisfactory compromise,
with interlacing used to double the apparent number of lines.
Picture and Synchronisation
The video carrier is demodulated to give a composite video signal;
this contains luminance (brightness), chrominance (color) and synchronisation signals;
this is identical to the video signal format used by analog video devices such as VCRs or CCTV cameras.
Note that the RF signal modulation is inverted compared to the conventional AM:
the minimum video signal level corresponds to maximum carrier amplitude, and vice versa.
The carrier is never shut off altogether; this is to ensure that intercarrier sound demodulation can still occur.
Each line of the displayed image is transmitted using a signal as shown below.
The same basic format (with minor differences mainly related to timing and the encoding of color)
is used for PAL, NTSC and SECAM television systems.
A monochrome signal is identical to a color one, with the exception that the elements shown in color in the diagram
(the color burst, and the chrominance signal) are not present.
Synchronisation
the front porch between the end of displayed video and the start of the sync pulse, and
the back porch after the sync pulse and before displayed video.
a nd represent the time that the electron beam in the CRT is returning to the start of the next display line.
The vertical sync signal is a series of much longer pulses, indicating the start of a new field.
The sync pulses occupy the whole of line interval of a number of lines at the beginning and end of a scan;
no picture information is transmitted during vertical retrace.
The pulse sequence is designed to allow horizontal sync to continue during vertical retrace;
it also indicates whether each field represents even or odd lines in interlaced systems
(depending on whether it begins at the start of a horizontal line, or mid-way through).
In the TV receiver, a sync separator circuit detects the sync voltage levels and sorts the pulses into horizontal and vertical sync.
These are fed to horizontal and vertical timebase circuits which generate sawtooth current waveforms,
which are each reset by the appropriate sync pulse.
These waveforms are fed to the horizontal and vertical scan coils wrapped around the CRT tube.
These produce a magnetic field proportional to the changing current,
and this deflects the electron beam, scanning it across the tube surface.
The lack of precision timing components available in early television receivers meant
that the timebase circuits occasionally needed manual adjustment.
The adjustment took the form of horizontal hold and vertical hold controls, usually on the rear of the set.
Loss of horizontal synchronisation usually resulted in an unwatchable picture;
loss of vertical synchronisation would produce an image rolling up or down the screen.
The timing for all this depends on the monitor refresh rate.
For a monitor with 60Hz refresh in 640x480 mode and a 25MHz pixel clock, you can use the timings in Figure 2.
The timings in this figure define the display time (the time when the pixel is one of the 640 visible pixels in a line),
pulse width (hSync or vSync), and the front porch and back porch timings.
These times (in μs or ms) can also be measured in terms of the number of ticks of the 25MHz pixel clock,
or in terms of the number of horizontal lines.
That is, the vertical timing can be measured in terms of how many hSync pulses have been seen.
The bottom line is that both the horizontal and vertical timing for the vgaControl are just counters.
You may have to enable things or reset things or change things when the counters get to a certain value,
but basically they’re just counters.
從上圖我們可以看到整個時序圖可以分為4段：
1，顯示階段，也就是video_on使能的階段。這個時候controlller要將RGB數據送給顯示器，而且是每一個pixel_clk送出一個pixel的RGB數據。
2，折回（retrace），也就是電子QIANG掃完一行之后回到最初掃描的位置用的時間。
3，前沿（front porch），之所以稱為前沿，是因為它在retrace的前面吧。對應於顯示右邊黑掉的部分。
4，后沿（back porch），對於與顯示左邊黑掉的部分。
Information is only displayed when the beam is moving in the “forward” direction (left to right and top to bottom),
and not during the time the beam is reset back to the left or top edge of the display.
Much of the potential display time is therefore lost in “blanking” periods
when the beam is reset and stabilized to begin a new horizontal or vertical display pass.
The size of the beams, the frequency at which the beam can be traced across the display,
and the frequency at which the electron beam can be modulated determine the display resolution.
VGA Timing Specification
Modern VGA displays can accommodate different resolutions,
and a VGA controller circuit dictates the resolution by producing timing signals to control the raster patterns.
The controller must produce synchronizing pulses at 3.3V (or 5V)
to set the frequency at which current flows through the deflection coils,
and it must ensure that video data is applied to the electron guns at the correct time.
Raster video displays define a number of “rows” that corresponds
to the number of horizontal passes the cathode makes over the display area,
and a number of “columns” that corresponds to an area on each row that is assigned to one “picture element”, or pixel.
Typical displays use from 240 to 1200 rows and from 320 to 1600 columns.
The overall size of a display and the number of rows and columns determines the size of each pixel.
Video data typically comes from a video refresh memory; with one or more bytes assigned to each pixel location
(the Nexys4 uses 12-bits per pixel, Nexys 2, Nexys 3 and Basys2 uses 8-bits).
The controller must index into video memory as the beams move across the display,
and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel.
A VGA controller circuit must generate the HS and VS timings signals
and coordinate the delivery of video data based on the pixel clock.
The pixel clock defines the time available to display one pixel of information.
The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn.
The minimum refresh frequency is a function of the display's phosphor and electron beam intensity,
with practical refresh frequencies falling in the 50Hz to 120Hz range.
The number of lines to be displayed at a given refresh frequency defines the horizontal “retrace” frequency.
顯示有兩個主要時間脈沖--垂直同步脈沖和水平同步脈沖，分別用於控制幀顯示與行顯示。
垂直同步脈沖有三部分組織:
1）垂直同步脈沖開始時序-Vertical back porch（VBP）表示垂直同步脈沖開始到一幀的有效像素數據開始前的一段時序，也表示有效像素數據開始時不顯示的行數。
2）垂直同步脈沖幀時序-Vertical active line（VACTL）表示一幀的有效像素數據開始前到一幀結束的時序，也表示有效像素數據行數。
2）垂直同步脈沖結束時序-Vertical front porch（VFP）表示一幀的有效像素數據開始結束后到下一幀同步脈沖開始前的時序，也表示有效像素數據結束后不顯示的行數。
水平同步脈沖有三部分組織:
1）水平同步脈沖開始時序-Horizontal back porch（HBP）表示水平同步脈沖開始到一行的有效像素數據開始前的一段時序，也表示有效像素數據開始時不顯示的像素個數。
2）水平同步脈沖行時序-Horizontal active line（HACTL）表示一行的有效像素數據開始前到一行結束的時序，也表示有效像素數據像素個數。
2）水平同步脈沖結束時序-Horizontal front porch（HFP）表示一行的有效像素數據開始結束后到下一行同步脈沖開始前的時序，也表示有效像素數據結束后不顯示的像素個數。
linux內核中的lcd參數
VBPD(vertical back porch)：表示在一幀圖像開始時，垂直同步信號以后的無效的行數，對應驅動中的upper_margin；
VFBD(vertical front porch)：表示在一幀圖像結束后，垂直同步信號以前的無效的行數，對應驅動中的lower_margin；
VSPW(vertical sync pulse width)：表示垂直同步脈 沖的寬度，用行數計算，對應驅動中的vsync_len；
HBPD(horizontal back porch)：表示從水平同步信號開始到一行的有效數據開始之間的VCLK的個數，對應驅動中的left_margin；
HFPD(horizontal front porth)：表示一行的有效數據結束到下一個水平同步信號開始之間的VCLK的個數，對應驅動中的right_margin；
HSPW(horizontal sync pulse width)：表示水平同步信號的寬度，用VCLK計算，對應驅動中的hsync_len；
A VGA driver isn't actually as complicated as you think.
All it really does is maintain counters for the X and Y positions.
Based on these counters, it knows when to send synchronization pulses to the display
and when to actually display pixels. Here is a timing diagram of the process (not to scale):
Here are the corresponding 640x480@60Hz VGA timing tables from tinyvga.com:
Each of the intervals shown have different timings depending on the resolution and refresh rate you decide to display at.
In the demo's case, it uses a modest 640x480 pixel display running at 60 Hz.
The timing for this mode all revolves around a special clock value, specifically 25.175 MHz.
This particular clock frequency allows each pulse to represent exactly one pixel.
From now on I will refer to this as the pixel clock.
In my implementation, I actually use a 25 MHz clock instead (easier to synthesize based off of internal oscillator).
Vertical timing is measured in scanlines and horizontal timing in pixels.
In the vertical front porch, there are 10 scanlines or 8000 pixels.
The usage of "pixels" is contextually dependent when talking about VGA.
VGA is all about timing, so when talking about pixels not in the display area, we are really referring to a unit of time.
Knowing the total horizontal and vertical lengths, the refresh rate is defined as:
We can easily calculate the VGA driver's refresh rate:
(25,000,000)/(800*525) ~= 60Hz.
This is pretty close to 60 Hz, even though the 640x480@60Hz specification states
a 25.175 MHz clock, my test monitor doesn't seem to mind.
顯示器掃描方式分為逐行掃描和隔行掃描：
逐行掃描是掃描從屏幕左上角一點開始，從左像右逐點掃描，每掃描完一行,電子束回到屏幕的左邊下一行的起始位置，
在這期間，CRT對電子束進行消隱，每行結束時，用行同步信號進行同步；
當掃描完所有的行，形成一幀，用場同步信號進行場同步，並使掃描回到屏幕左上方，同時進行場消隱,開始下一幀。
隔行掃描是指電子束掃描時每隔一行掃一線，完成一屏后在返回來掃描剩下的線，隔行掃描的顯示器閃爍的厲害，會讓使用者的眼睛疲勞。
完成一行掃描的時間稱為水平掃描時間，其倒數稱為行頻率；
完成一幀（整屏）掃描的時間稱為垂直掃描時間，其倒數稱為場頻率，
即刷新一屏的頻率，常見的有60Hz，75Hz等等。
標准的VGA顯示的場頻60Hz,行頻31.5KHz。
顯示帶寬:帶寬指的顯示器可以處理的頻率范圍。
如果是60Hz刷新頻率的VGA,其帶寬達640x480x60=18.4MHz,
70Hz的刷新頻率1024x768分辨率的SVGA,其帶寬達1024x768x70=55.1MHz。
時鍾頻率：以640x480@59.94Hz(60Hz)為例，每場對應525個行周期(525=10+2+480+33),其中480為顯示行。
每場有場同步信號,該脈沖寬度為2個行周期的負脈沖，
每顯示行包括800點時鍾,其中640點為有效顯示區,
每一行有一個行同步信號，該脈沖寬度為96個點時鍾。
由此可知：行頻為525*59.94=31469Hz,需要點時鍾頻率：525*800*59.94約25MHz.
一、VGA時序分析：
VESA中定義行時序和場時序都需要同步脈沖
（Sync a）、顯示后沿（Back porch b）、顯示時序段（Display interval c）和顯示前沿（Front porch d）四部分。
VGA工業標准顯示模式要求：行同步，場同步都為負極性，即同步脈沖要求是負脈沖。
由VGA的行時序可知：
每沒一行都有一個負極性行同步脈沖（Sync a），是數據行的結束標志，同時也是下一行的開始標志。
在同步脈沖之后為顯示后沿（Back porch b），在顯示時序段（Display interval c）顯示器為亮的過程，
RGB數據驅動一行上的每一個像素點，從而顯示一行。
在一行的最后為顯示前沿（Front porch d）。
在顯示時間段（Display interval c）之外沒有圖像投射到屏幕是插入消隱信號。
同步脈沖(Sync a)、顯示后沿（Back porch b）和顯示前沿（Front porch d）都是在行消隱間隔內
(Horizontal Blanking Interval)，當消隱有效時，RGB信號無效，屏幕不顯示數據。
VGA的場時序與行時序基本一樣，每一幀的負極性脈沖（Sync a）是一幀的結束標志，
同時也是下一幀的開始標志。而顯示數據是一幀的所有行數據。
下面以800x600@60Hz分辨率為例子詳細講解VGA時序:
GENERATING VGA (video graphics array)
The first VGA display was introduced with the IBM PS/2 line of computers in 1987.
One thing most people associate with this form of display is the 15-pin D-subminiature VGA connector
you tend to find on the back of a tower computer or the side of your notebook computer.
The original VGA standard supported a resolution of only 640×480
(which means 640 pixels in the horizontal plane and 480 lines in the vertical plane).
Over the years, however, the standard has evolved to support a wide variety of resolutions,
all the way up to widescreen resolutions as high as 1920×1080.
The act of driving a VGA is surprisingly simple, being based on the use of two counters as follows:
- Pixel counter:
Counts at the required clock frequency (40MHz in this example) the number of pixels in a line, this is used to generate the horizontal timing. - Line counter:
Also known as the Frame Counter, this repeats at the refresh rate of the desired VESA specification
for 60Hz, 75Hz, 85Hz, and so on. This also identifies when the counter is within a valid region for outputting display data.
The line counter is incremented each time the pixel counter reaches its terminal count.
These counters are used to generate two synchronization (sync) markers —
the “V_Sync” (vertical sync) and “H_Sync” (horizontal sync) signals.
In conjunction with the RGB (red, green, and blue) analog signals ,
“V_Sync” and “H_Sync” form the basic signals required to display video on a monitor.
Actually, this may be a good time to take a step back to remind ourselves as to
the origin of terms like “V_Sync” and “H_Sync.”
The main thing to remember is that, at the time the original VGA standard was introduced,
the predominant form of computer display was based on the cathode ray tube (CRT),
in which an electron beam is used to “write” on a phosphorescent screen.
There are several ways in which an electron beam can be manipulated to create images on a CRT screen,
but by far the most common technique is the raster scan.
Using this approach, the electron beam commences in the upper-left corner of the screen
and is guided across the screen to the right.
The path the beam follows as it crosses the screen is referred to as a line.
When the beam reaches the right-hand side of the screen it undergoes a process known as horizontal flyback,
in which its intensity is reduced and it is caused to “fly back” across the screen.
While the beam is flying back it is also pulled a little way down the screen as shown in the following illustration:
The beam is now used to form a second line, then a third, and so on until it reaches the bottom of the screen.
The number of lines affects the resolution of the resulting picture (that is, the amount of detail that can be displayed).
When the beam reaches the bottom right-hand corner of the screen it undergoes vertical flyback,
in which its intensity is reduced, it “flies back” up the screen to return to its original position
in the upper left-hand corner, and the whole process starts again.
The “V_Sync” and “H_Sync” signals are used to synchronize all of these activities.
Thus, returning to our pixel and line counters, the values on these counters
can be decoded so as to generate the required waveforms on the “V_Sync” and “H_Sync”
outputs from an FPGA (that is, on the FPGA’s pins that are being used to drive the display’s “V_Sync” and “H_Sync” signals).
Meanwhile, generating the RGB signals will require the FPGA to drive three digital-to-analog convertors (DACs), one for each signal.
As the design engineer, you must ensure that the latency through the DACs is accounted for to ensure
that their outputs are correctly aligned with respect to the “V_Sync” and “H_Sync” signals.
The line and pixel counters both have portions of their count sequences
when no data is being output to the display.
In the case of an 800×600 resolution display refreshing at 60Hz,
for example, the vertical (line) counter will actually count 628 lines
while the horizontal (pixel) counter will count 1,056 pixels.
Why should this be so?
Well, returning to our raster scan, it takes a certain amount of time for the electron beam
to undergo its horizontal and vertical flyback activities.
One way to think about these times is that we have an actual display area that we see,
and that this actual display area “lives” in a larger (virtual) display space that contains a border zone that we don’t see:
Of course, in the case of today’s flat-screen, liquid crystal displays (LCDs) and similar technologies,
we don’t actually need to worry about things like horizontal and vertical flyback times.
At least, we wouldn’t have to worry if it were not for the fact that we don’t actually know
what type of screen our FPGA is driving.
Thus, anything driving a VGA output generates the timing signals required to drive CRT display,
and other forms of display simply make allowances for any of the historical peculiarities associated with these VGA signals.
But we digress… Each of our counters has a collection of associated timing parameters.
Vertical timings are referenced in terms of lines, while horizontal timings are referenced in terms of pixels.
The following table lists timing values for several popular resolutions.
| Format | Pixel Clock (MHz) |
Horizontal (in Pixels) | Vertical (in Lines) | ||||||
|---|---|---|---|---|---|---|---|---|---|
| Active Video |
Front Porch |
Sync Pulse |
Back Porch |
Active Video |
Front Porch |
Sync Pulse |
Back Porch |
||
| 640x480, 60Hz | 25.175 | 640 | 16 | 96 | 48 | 480 | 11 | 2 | 31 |
| 640x480, 72Hz | 31.500 | 640 | 24 | 40 | 128 | 480 | 9 | 3 | 28 |
| 640x480, 75Hz | 31.500 | 640 | 16 | 96 | 48 | 480 | 11 | 2 | 32 |
| 640x480, 85Hz | 36.000 | 640 | 32 | 48 | 112 | 480 | 1 | 3 | 25 |
| 800x600, 56Hz | 38.100 | 800 | 32 | 128 | 128 | 600 | 1 | 4 | 14 |
| 800x600, 60Hz | 40.000 | 800 | 40 | 128 | 88 | 600 | 1 | 4 | 23 |
| 800x600, 72Hz | 50.000 | 800 | 56 | 120 | 64 | 600 | 37 | 6 | 23 |
| 800x600, 75Hz | 49.500 | 800 | 16 | 80 | 160 | 600 | 1 | 2 | 21 |
| 800x600, 85Hz | 56.250 | 800 | 32 | 64 | 152 | 600 | 1 | 3 | 27 |
| 1024x768, 60Hz | 65.000 | 1024 | 24 | 136 | 160 | 768 | 3 | 6 | 29 |
| 1024x768, 70Hz | 75.000 | 1024 | 24 | 136 | 144 | 768 | 3 | 6 | 29 |
| 1024x768, 75Hz | 78.750 | 1024 | 16 | 96 | 176 | 768 | 1 | 3 | 28 |
| 1024x768, 85Hz | 94.500 | 1024 | 48 | 96 | 208 | 768 | 1 | 3 | 36 |
| Source: Rick Ballantyne, Xilinx Inc. | |||||||||
Principles of VGA Video
There are three signals -- red, green, and blue (RGB) -- that send color information to a VGA monitor.
Signal levels between 0 (completely dark) and 0.7 V (maximum brightness) control the intensity of each color component,
which combine to make the final color of a pixel on the monitor screen.
Each analog color input can be set to one of 32 levels by five digital outputs using a simple five-bit digital-to-analog converter (DAC) as shown below.
Replicating the DAC for each analog input gives us a palette of 32 x 32 x 32 = 32768 different colors selectable through fifteen digital control lines.
For many applications we only need two colors:
black and white.
This is done by applying the same level to each of the RGB inputs.
This simplifies the DAC circuitry to a single resistor driven by a single output.
An image (or frame) on a monitor screen is composed of h lines each containing w pixels.
VGA frame size is expressed as w x h with typical sizes of 640 x 480, 800 x 600, 1024 x 768 and 1280 x 1024.
In order to send a frame of pixels to the monitor, two sync signals are required:
a horizontal sync to indicate the start and stop of each line of pixels going from left to right on the screen,
and a vertical sync that marks the top and bottom lines so they stack up to form an image.
The timing for the VGA sync signals is shown in below.
Negative pulses on the horizontal sync signal mark the start and end of a line and ensure that the monitor displays the pixels
between the left and right edges of the visible screen area.
The pixels are sent on the RGB signal lines within a 25.17 μs window.
After this, a front porch interval of 0.94 μs is inserted before the horizontal sync signal goes low for 3.77 μs.
After a back porch interval of 1.89 μs, the next line of pixels begins.
Therefore, a single line of pixels occupies 25.17 μs of a 31.77 μs interval.
The red, green and blue signals are blanked during the 6.6 μs interval comprised of the front porch, sync pulse and back porch.
In a similar fashion, negative pulses on the vertical sync signal mark the start and end of a frame of video lines
and ensure that the monitor displays the lines between the top and bottom edges of the visible monitor screen.
The lines are displayed within a 15.25 ms window.
After this, a front porch interval of 0.45 ms is inserted before the vertical sync signal goes low for 64 μs.
After a back porch interval of 1.02 ms, the next frame begins.
Therefore, a single frame of pixels occupies 15.25 ms of a 16.784 ms interval.
The RGB signals are blanked during the 1.534 ms interval comprised of the front porch, sync pulse and back porch.
The pixel clock rate needs to be adjusted to achieve Vsync rates and Hsync rates that are acceptable for your multisync monitor.
Since 40Hz is not a common Vsync rate, try 30, 50 or 60 or higher.
640*480 * 40Hz = 12.3MHz so it seems pixels are pushed out at 1/2 of 25MHz clock rate
The NTSC timing for V Sync , front porch (480~494) , Hsync, back porch(495~525) as follows using 25MHz
Hsync can be varied as long with before after periods as long as sum is same.
Some monitors have a 10% tolerance depending design.
LCD bus timing parameters
Frame and line timing parameters
How VGA Monitors Work
The VGA monitor can be thought of as a grid of pixels (picture elements which can be individually set to a specific colour).
It contains 480 rows of 640 horizontal pixels. Most monitors, including VGA, use a serial scheme to set the colour of each pixel.
This means that the VGA controller sends the colour information for each pixel one at a time,
rather than being able to set all of the colours at once in a parallel scheme.
This colour information for each pixel is provided by a RGB (Red, Green, Blue) triplet.
Three analog signals are used to represent relative amounts of red, green, and blue that compose the colour.
However, the UP2 board produces digital signals.
Thus, the controller is only able to provide full intensity or turn off for each of the RGB components.
The VGA monitor does not save any of the pixels written to it so the pixels
must be continuously written to the monitor for the image to remain stable.
The protocol for the transmission is shown below.
The horizontal cycle is part of the VGA standard and defines a method for setting the colours of all the pixels in a particular row.
The colour values for the 640 pixels are sent out on each of the first 640 clock cyles.
The colour values are then forced to zero (black), while the hsync signal is asserted low
to tell the monitor to move to the next horizontal row of pixels.
The exact timing between these signals is defined in the VHDL source code for the VGA controller.
The VGA controller only allows your requests to write pixels while the colour signals are forced to zero.
At all other times, it is reading from memory and it cannot write to the memory at the same time.
The vertical cycle allows the monitor to synchronize which rows are being written by the horizontal cycles.
480 horizontal cycles are produced during the first stage of the vertical cycle.
In the next stage, the colour values are again forced to zero (black), while the vsync signal is asserted.
The vsync signal tells the monitor to go back to the (0,0) pixel.
The data that follows starts with the first horizontal row of pixels.
LCD TFT Display Controller (LTDC)
The LCD TFT display controller provides a parallel digital RGB (Red, Green, Blue)
and signals for horizontal, vertical synchronisation, Pixel Clock and Data Enable
as output to interface directly to a variety of LCD and TFT panels.
LCD display configuration
DLPC343x Display Controller Video Timing Parameter Definitions
Note: HBP times are reference to the leading (active) edge of the respective sync signal.
Horizontal Front Porch (HFP) BlankingNumber of blank pixel clocks after the last active pixel but before Horizontal Sync.
The absolute reference point is defined by the active edge of the HS signal.
The active edge (either rising or falling edge as defined by the source) is the reference from which all horizontal blanking parameters are measured.
The absolute reference point is defined by the active edge of the VS signal.
The active edge (either rising or falling edge as defined by the source) is the reference from which all vertical blanking parameters are measured.
