VHDL之Port map and open

　　編SPI的master控制器，使用公司基本的元件，有些端口用不着，恰巧好二哥(不知年齡的數字組組長，本名Holger)來了，於是請教之，告曰open關鍵詞。后來深感自己VHDL水平太水，下了一本電子書惡補語法。明白了open，順帶了port mapping

<<Circuit Design With VHDL>> chapter 10, 10.4

　　Two ways to map the PORTS of a COMPONENT during its instantiation:

1　　Positional mapping, ports x and y correspond to a and b, respectively.

COMPONENT inverter IS
    PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC); 
END COMPONENT; 
... 

U1 : inverter PORT MAP (X,Y);

 2　　 Nominal mapping would be the following:

U1: inverter PORT MAP (x => a, y => b);

  Positional mapping is easier to write, but nominal mapping is less error-prone.

  

 3　　Ports can also be left unconnected (using the keyword OPEN). 

U2: my_circuit PORT MAP (X => a, y => b, z => OPEN);

4　　=>  used to assign values to individual vector or with keyword others

signal Data_Bus : std_logic_vector (15 downto 0);
... ...

-- 1st way
Data_Bus <= (15 | 7 downto 0 => '1', others => '0');

-- 2nd way
Data_Bus (15 | 7 downto 0) <= '1';
Data_Bus (14 downto 8) <= '0';