1、Warning (10227): Verilog HDL Port Declaration warning at PRESS_MODELE.v(29): data type declaration for "iR" declares packed dimensions but the port declaration declaration does not.
解釋：
2、Warning: PLL "DE2_TV:inst1|Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|pll" output port clk[0] feeds output pin "DRAM1_CLK" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
解釋：PLL的輸出用在了非專屬的PLL_OUT
措施：設計電路板的時候最好將PLL_OUT用在相關的時鍾信號上，如果沒有使用，則這個警告不理會也可。
3、Warning: Using design file cpu.v, which is not specified as a design file for the current project, but contains definitions for 25 design units and 25 entities in project
解釋：模塊不是在本項目生成的，而是直接copy了別的項目的原理圖和源程序生成的，不是用QUARTUS將文件添加進本項目
措施：無須理會，不影響使用
4、Warning (10240): Verilog HDL Always Construct warning at I2C_V_Config.v(153): inferring latch(es) for variable "LUT_DATA", which holds its previous value in one or more paths through the always construct
解釋：信號被綜合成了latch，鎖存器的EN和數據輸入端口存在一個競爭的問題
措施：將計數器從里面抽出來
5、Warning: 12 hierarchies have connectivity warnings - see the Connectivity Checks report folder
解釋：實例化的時候，有一些端口沒用，讓沒用的端口的位置空着，
措施：不用理會
6、Warning: Synthesized away the following node(s)
解釋：以下節點被綜合優化掉
措施：不用理會
7、Warning:Found xx output pins without output pin load capacitance assignment
解釋：沒有給輸出管教指定負載電容
措施：該功能用於估算TCO和功耗，可以不理會，也可以在Assignment Editor中為相應的輸出管腳指定負載電容，以消除警告
8、Warning: The following nodes have both tri-state and non-tri-state drivers
解釋：該用三態邏輯驅動的信號，被用非三態邏輯驅動了
措施：在子信息中定位到警告所在，改用三態邏輯驅動
9、Warning: Latch DE2_TV:inst1|I2C_V_Config:I2C_AV_Config|LUT_DATA[8] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal DE2_TV:inst1|I2C_V_Config:I2C_AV_Config|LUT_INDEX[4]
解釋：產生了latch
措施：用時序代替組合電路，或者是用完備的if/else，和case語句
10、Warning: TRI or OPNDRN buffers permanently enabled
解釋：輸出要加三態控制
11、Warning: Output pins are stuck at VCC or GND
解釋：這幾個輸出管腳直接接地了
措施：如果這符合你的設計要求這種警告可以不管
12、Warning (15400): WYSIWYG primitive "DE2_TV:inst1|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_21m1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a15" has a port clk1 that is stuck at GND
解釋：這里是采用的SDRAM的讀寫方式為1入2出的模式，將fifo2的輸入信號給接GND了
措施：不用理會。
另外：如果出現跟RAM相關的WYSIWYG primitive錯誤或者是警告，則是RAM的輸入端信號不通導致。
13、Warning: Design contains 2 input pin(s) that do not drive logic
解釋：有2個輸入沒有驅動任何邏輯，也就是說，只定義了2個輸入管腳，但在邏輯中並沒有使用這2個輸入信號
措施：將這2個輸入管腳的定義去掉即可
14、Warning: At least one of the filters had some problems and could not be matched.
解釋：
措施：
15、Warning: Node: XXX was determined to be a clock but was found without an associated clock assignment.
解釋及措施：
(1). 這個信號是不是你期望的時鍾信號？還是被綜合器誤將普通信號綜合成了時鍾信號？有沒有在代碼中用過這個信號的上升沿/下降沿？
(2). 如果是期望的時鍾信號，那么是否有可能調整管腳位置約束到專用時鍾管腳？如果不行的話，這條時鍾線上的延時會比較大。但是整個布局布線還是可以進行下去的。
16、Warning: PLL "DE2_TV:inst1|Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|pll" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins
解釋：
措施：
17、Warning: PLL "DE2_TV:inst1|Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|pll" output port clk[0] feeds output pin "DRAM1_CLK" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
解釋：這是說沒有使用FPGA專用的PLL輸出引腳
措施：同2
18、Warning: Ignored locations or region assignments to the following nodes
Warning: Node "FIELD" is assigned to location or region, but does not exist in design
解釋：有些引腳做了分配，但是在設計中沒有使用
措施：可以不用理會
19：Warning: Following 1 pins have no output enable or a GND or VCC output enable - later changes to this
connectivity maychange fitting results
解釋：下面有1個管腳沒有輸出使能，或者僅僅是GND，VCC使能
措施：給其配置一個使能即可
20、Warning: Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may
change fitting results
解釋：同11
措施：同11
21、Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving
ground'.
解釋：所有沒有用到的管腳都直接接GND
措施：可以不用理會，也可以在 Assignments 里做修改