Port Definitions
control signals
// common
input rdpath_rdy,
output reg prech_done,
output reg dfi_init_complete,
// write leveling
input wrlvl_done,
input wrlvl_rank_done,
output reg wrlvl_active,
// read leveling
input rdlvl_done,
output reg [1:0] rdlvl_start,
input rdlvl_clkdiv_done,
output reg rdlvl_clkdiv_start,
input rdlvl_prech_reg,
input rdlvl_resume,
// Read phase detector calibration control
output reg pd_cal_start,
input pd_cal_done,
input pd_prech_reg
DFI signals
// PHY DFI address/control
output reg [ROW_WIDTH-1:0] phy_address0,
output reg [ROW_WIDTH-1:0] phy_address1,
output reg [BANK_WIDTH-1:0] phy_bank0,
output reg [BANK_WIDTH-1:0] phy_bank1,
output reg phy_cas_n0,
output reg phy_cas_n1,
output reg [CKE_WIDTH-1:0] phy_cke0,
output reg [CKE_WIDTH-1:0] phy_cke1,
output reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_cs_n0,
output reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_cs_n1,
output phy_init_data_sel,
output reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_odt0,
output reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_odt1,
output reg phy_ras_n0,
output reg phy_ras_n1,
output reg phy_reset_n,
output reg phy_we_n0,
output reg phy_we_n1,
// PHY DFI Write
output reg phy_wrdata_en,
output reg [4*DQ_WIDTH-1:0] phy_wrdata,
// PHY DFI Read
output reg phy_rddata_en,
// PHY sideband signals
output reg [0:0] phy_ioconfig,
output reg phy_ioconfig_en
Code Blocks
Mode register programming
//*****************************************************************
// DDR3 Load mode reg0
// Mode Register (MR0):
// [15:13] - unused - 000
// [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit),
// 1 (DLL maintained)
// [11:9] - write recovery for Auto Precharge (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4],[2] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [1:0] - Burst Length - BURST_LEN
// DDR2 Load mode register
// Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - Power-down mode - 0 (normal)
// [11:9] - write recovery - write recovery for Auto Precharge
// (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [2:0] - Burst Length - BURST_LEN
//*****************************************************************
//*****************************************************************
// DDR3 Load mode reg1
// Mode Register (MR1):
// [15:13] - unused - 00
// [12] - output enable - 0 (enabled for DQ, DQS, DQS#)
// [11] - TDQS enable - 0 (TDQS disabled and DM enabled)
// [10] - reserved - 0 (must be '0')
// [9] - RTT[2] - 0
// [8] - reserved - 0 (must be '0')
// [7] - write leveling - 0 (disabled), 1 (enabled)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7)
// [4:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7)
// [0] - DLL enable - 0 (normal)
// DDR2 ext mode register
// Extended Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - output enable - 0 (enabled)
// [11] - RDQS enable - 0 (disabled)
// [10] - DQS# enable - 0 (enabled)
// [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced)
// [0] - DLL enable - 0 (normal)
//*****************************************************************
//*****************************************************************
// DDR3 Load mode reg2
// Mode Register (MR2):
// [15:11] - unused - 00
// [10:9] - RTT_WR - 00 (Dynamic ODT off)
// [8] - reserved - 0 (must be '0')
// [7] - self-refresh temperature range -
// 0 (normal), 1 (extended)
// [6] - Auto Self-Refresh - 0 (manual), 1(auto)
// [5:3] - CAS Write Latency (CWL) -
// 000 (5 for 400 MHz device),
// 001 (6 for 400 MHz to 533 MHz devices),
// 010 (7 for 533 MHz to 667 MHz devices),
// 011 (8 for 667 MHz to 800 MHz)
// [2:0] - Partial Array Self-Refresh (Optional) -
// 000 (full array)
// Not used for DDR2
//*****************************************************************
//*****************************************************************
// DDR3 Load mode reg3
// Mode Register (MR3):
// [15:3] - unused - All zeros
// [2] - MPR Operation - 0(normal operation), 1(data flow from MPR)
// [1:0] - MPR location - 00 (Predefined pattern)
//*****************************************************************
State machine
Segment 1
INIT_IDLE:Initial state, wait for:
1.Power-on delays to pass
2.Read path initialization to finish
INIT_WAIT_CKE_EXIT: tXPR: wait time after CKE deassertion before first MRS command can be asserted
Segment 2
When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the
MRS command is issued.
tMRD is the minimum time between two MRS command
ZQ Calibration command is used to calibrate DRAM Ron & ODT values. DDR3 SDRAM needs longer time to calibrate output driver and on-die termination circuits at initialization and relatively smaller time to perform periodic calibrations.
INIT_WAIT_DLLK_ZQINIT:Wait for both DLL to lock (tDLLK) and ZQ calibration to finish (tZQINIT)
Segment 3
INIT_WRLVL_START: Enable write leveling in MR1 and start write leveling
INIT_WRLVL_WAIT: wait for both MR load and write leveling to complete(wait for tMOD time after MRS to assert ODT.
INIT_WRLVL_LOAD_MR2: Load MR2 to set ODT