（一）
Modelsim报错：
Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./myadder_run_msim_gate_verilog.do PAUSED at line 12
网上有说解决办法有：1）在安装目录下把modelsim.ini文件的只读去掉，但我已经是只读了
2）license问题，没有破解好，但我做其他仿真的时候是好的
解决办法：在testbench中添加了一句`timescale 1ns/1ns
（二）
这个错误好像是因为已经开了一个modelsim，关掉再来就好了。
直接调用modelsim-altera得到了仿真波形。
（三）
** Warning: E:/modelsim/adder/simulation/modelsim/myadder.vo(85): Unable to access $sdf_annotate file pathname myadder_v.sdo for reading.
# ** Error: E:/modelsim/adder/simulation/modelsim/myadder.vo(1616): Module 'cyclone_lcell' is not defined.
# ** Error: E:/modelsim/adder/simulation/modelsim/myadder.vo(1644): Module 'cyclone_io' is not defined.
# Optimization failed
# Error loading design
没有添加.sdo文件。
（四）
# ** Error: (vsim-3033) E:/modelsim/adder/simulation/modelsim/myadder.vo(267): Instantiation of 'cyclone_io' failed. The design unit was not found.
# Region: /t/m
# Searched libraries:
# D:\modeltech_10.0c\win32\work
# ** Error: (vsim-3033) E:/modelsim/adder/simulation/modelsim/myadder.vo(310): Instantiation of 'cyclone_lcell' failed. The design unit was not found.
# Region: /t/m
# Error loading design
这是因为我编译的是cycloneii_atoms.v
（五）
# Compile of t.v failed with 1 errors.
# Compile of myadder.vo failed with 1 errors.
# Compile of cyclone_atoms.v failed with 1 errors.
这是因为work这个library被删掉了。
（六）
# ** Error: (vsim-7) Failed to open SDF file "myadder_v.sdo" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "myadder_v.sdo".
# Time: 0 ps Iteration: 0 Instance: /t File: E:/modelsim/adder/t.v
# Error loading design
解决：http://blog.chinaaet.com/detail/35266
将用QuartusII先生成的.sdo文件考到与工程名同目录下,工程名的后缀名为.mpf
（七）
# ** Error: E:/QUARTUS/ex9/sdram_mdl/sdr_test.v(148): 'syswr_done' already declared in this scope (sdr_test).
# ** Error: E:/QUARTUS/ex9/sdram_mdl/sdr_test.v(162): 'tx_start' already declared in this scope (sdr_test).
# ** Error: D:/modeltech_10.0c/win32/vlog failed.
# ** Error: E:/QUARTUS/ex9/sdram_mdl/sdram_ctrl.v(88): Undefined variable: cnt_clk_r.
# ** Error: E:/QUARTUS/ex9/sdram_mdl/sdram_ctrl.v(192): 'cnt_clk_r' already declared in this scope (sdram_ctrl).
# ** Error: D:/modeltech_10.0c/win32/vlog failed
通过把信号定义挪到调用模块前面问题解决